MONOLITHIC AND HERMETICALLY SEALED AND POSITIVE OUTPUTS
CQSJ
INCLOSURE MATERIAL
CERAMIC AND GLASS
CQSZ
INCLOSURE CONFIGURATION
DUAL-IN-LINE
CQWX
OUTPUT LOGIC FORM
TRANSISTOR-TRANSISTOR LOGIC
CQZP
INPUT CIRCUIT PATTERN
4 INPUT
CSSL
DESIGN FUNCTION AND QUANTITY
1 GATE, NAND
CTFT
CASE OUTLINE SOURCE AND DESIGNATOR
TO-116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL
CZEQ
TIME RATING PER CHACTERISTIC
29.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 15.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT
TEST
TEST DATA DOCUMENT
80063-SM-B-641498 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING
Relevant Components for NSN - 5962-00-245-1612, 5962002451612
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